Veri cation and Synthesis of Counters based on Symbolic Techniques

Symbolic Techniques have undergone major improvements but extending their applicability to new elds is still a key issue. A great limitation on standard Symbolic Traversals is represented by Finite State Machines with a very high sequential depth. A typical example of this behaviour are counters. On the other hand systems containing counters, e.g. embedded systems, are of great practical importance in several elds. Iterative squaring can produce solutions with a logarithmic execution time with respect to the sequential depth but a few drawbacks usually limit its application. We successfully tailored iterative squaring to allow its application for symbolic veri cation and synthesis of circuits containing counters. Experiments on large and complex home{made and industrials circuits containing counters show the feasibility of the approach.